Recent questions tagged assembly

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assembly - Does a function with instructions before the entry-point label cause problems for anything (linking)?

This is really a linker / object-file question, but tagging with assembly since compilers never do this. ( ... true, though, for Nehalem. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Why in NASM do we have to use square brackets ([ ]) to MOV to memory location?

For example if I have a variable named test declared like: test db 0x01 ;suppose the address is 0x00000052 If ... the first or second operands? See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - What's the real meaning of $$ in nasm

$$ is defined as current segment address in NASM. But what's the real meaning of it? I wrote two asm files ... with them? Thanks a lot! See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Why don't x86 16-bit addressing modes have a scale factor, while the 32-bit version has it?

I'm trying to figure out a reason for the scale factor not being present in the x86 16-bit addressing modes ... 16- and 32-bit addressing modes See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Why does my data section appear twice in the compiled binary? Ubuntu, x86, nasm, gdb, reaelf

A prior related question was answered. Thank you! However this creates a new question for me. Why does nasm ... two different locations? Why? See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Why "DIV EDX" in MASM always generates processor exception?

I've got that question on my Computer Architecture Exam on Informatics last semester : "Why 'DIV EDX' ... mechanism which generates exception? See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - How do GNU assembler x86 instruction suffixes like ".s" in "mov.s" work?

GNU assembler appears to have some means of controlling the alternative forms of the opcode being emitted for ... any relevant documentation. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Cannot call real mode C function from bootloader (NASM + GCC toolchain)

I am attempting to write my own OS kernel, and have been having some issues getting the linking to work properly ... Correct me if I'm wrong. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Hard to debug SEGV due to skipped cmov from out-of-bounds memory

I'm trying to code a few high-performance assembly functions as an exercise, and have encountered a weird segfault ... Thanks for all the help. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - What comes after QWORD?

If 8 bits is a byte two bytes is a word four bytes is a dword 8 bytes is a qword What is a good name for 16 bytes? See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - What is the significance of operations on the register EAX having their own opcodes?

If you look at documentation of operations like cmp, test, add, sub, and and, you will notice that ... shaking off for compatibility reasons? See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Should pointer comparisons be signed or unsigned in 64-bit x86?

When writing x86-64 user-space assembly and comparing two pointer values, should we use signed conditions such as ... top of the address space. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Embed assembler to manipulate 64-bit registers in portable C++

I have a simple (but performance critical) algorithm in C (embedded in C++) to manipulate a data buffer... the ... (please pardon the pun...)? See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - On x64 Linux, what is the difference between syscall, int 0x80 and ret to exit a program?

I decided yesterday to learn assembly (NASM syntax) after years of C++ and Python and I'm already confused about the ... best way. I'm curious. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Detail about MSR_GS_BASE in linux x86 64

I tried to figure out the details of MACRO current in Linux kernel. The final assembly code of current is: ... need some references about this. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Encoding ADC EAX, ECX - 2 different ways to encode? (arch x86)

I'm looking through an Intel Instruction Set manual, and it looks like there are 2 different forms of ADC ... attempts at googling it failed. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - What's the easiest way to determine if a register's value is equal to zero or not?

I'm using x86 assembly with the Irvine library. What's the easiest way to check if a register value is equal to zero ... ebx = !!ebx would in C. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - I don't understand how to use Interrupt 21, AH=0ah

My information is coming from here. The assignment asks for a program that reads in no more than 20 characters, ... '$' code ends end start See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - What is the ".s" suffix in x86 instructions?

When I disassemble the .text sections of some binaries using objdump (with both AT&T and Intel syntaxes), I ... of instructions? Thank you. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Are ARM instructuons SWI and SVC exactly same thing?

ARM assembly has SWI and SVC instructions for entering into 'supervisor mode'. What confuses me is, why there ... architecture, and other after? See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - How to store a two-register mul result into memory

So let's say that I've got a result of mul in dx:ax, how can I save it to dword [ebx]?? I have the ... half) to two dwords pointed to by [ebx]. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Does a memory barrier acts both as a marker and as an instruction?

I have read different things about how a memory barrier works. For example, the user Johan's answer in this ... memory barrier. Am I correct? See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Reverse byte order of EAX register

Example: 0xAABBCCDD will turn into 0xDDCCBBAA My program crashes, due to Access Violation exception right in the ... better solution for this? See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Convert string to int. x86 32 bit Assembler using Nasm

So I'm trying to convert a string to a number so I can add another number to it later. here is what I have ... ax, '0' add [Num1plusNum2], ax See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Why do x86 jump/call instructions use relative displacements instead of absolute destinations?

I am learning 8086 and there is one particular question which is bothering me and I have not been able to find ... this design choice in 8086? See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - Cannot move 8 bit address to 16 bit register

I am trying to assign variable to register here is the code: ORG 100h var1 DB 10 ; var2 DB 20 ; MOV BX, ... apologise if it's a stupid question. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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assembly - What is the compatible subset of Intel's and AMD's x86-64 implementations?

While learning x86-64 assembly, I came across my first incompatibility between Intel 64 and AMD64 implementations of ... or some third party See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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700 views

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assembly - Does Skylake need vzeroupper for turbo clocks to recover after a 512-bit instruction that only reads a ZMM register, writing a k mask?

Writing a ZMM register can leave a Skylake-X (or similar) CPU in a state of reduced max-turbo ... AVX512BW excludes KNL is irrelevant. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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